1. Field of the Invention
The present invention relates to standard cells which is a type of semi-custom LSI and more particularly, to such standard cells which include flip-flop circuits.
2. Description of the Background Art
In designing the placement and routing of certain types of logical circuits in standard cells, care must be taken to avoid possible malfunctions.
In particular when the standard cell involves flip-flops, considerations must be given to take care of malfunctions due to so-called clock-skew and racing.
First, clock-skew will be explained with references to FIGS. 1 and 2. In a shift register shown in FIG. 1. a clock signal CLK1 for a first flip-flop FF1 and a clock signal CLK2 for a second flip-flop FF2 have, as shown in FIG. 2, a phase difference called skew due to presence of routing resistance R and routing capacitance C in a clock routing CLK between the first and second flip-flops FF1 and FF2. The appearance of such a skew in clock signal is called clock-skew. Since the longer routing makes more delay of a transmission of a clock signal between two flip flops, it is desirable for the flip-flops to have the routing for the clock signal as short as possible.
Next, racing will be explained with further references to FIGS. 3, 4 and 5. Again, in the shift register of FIG. 1, when there is a large clock-skew while there is only a short routing between an output terminal Q of the first flip-flop FF1 and an input terminal D of the second flip-flop FF2, the switching of data at the input terminal D of the second flip-flop FF2 will occur before a switching of the clock at a point h, because a delay of data in going from the first flip-flop FF1 to the second flip-flop FF2 will be smaller than a delay of clock signal due to the clock-skew As a result as shown in FIG. 3, while a clock at a point g switches when data in a routing d is a.sub.1 so that the first flip-flop FF1 receives data a.sub.1, a corresponding clock at a point h switches so much later that data in a routing e has already switched from a.sub.0 to a.sub.1 by the time a clock at a point h switches so that the second flip-flop FF2 also receives the same data a.sub.1 at the same timing, causing an erroneously premature output of data a.sub.1 in a routing f. This phenomenon is called racing.
Conventionally, racing is avoided by providing an extra delay X between the output terminal Q of the first flip-flop FF1 and the input terminal D of the second flip-flop FF2 as shown in FIG. 4, such that a delay of data is suitably elongated to be compatible with a delay of clock due to the clock-skew so as to achieve a correct timing relationship shown in FIG. 5 in which the output in the routing f is correctly a.sub.0.
Although this type of prevention of the racing by means of an extra delay between two flip-flops is very common, there is a tendency to use a delay with unnecessarily long delay time for such an extra delay, as a safety measure for the general situation where the length of the clock routing which determines an amount of clock-skew is not known precisely before the cell placing and routing. Furthermore, when another logical circuit, such as a combinational circuit, is to be connected between two flip-flops in addition to the delay, an actual operation time will be limited not only by the time for clock skew and the delay time of the delay but also by an access time of the combinational circuit, so that a severe limitation is posed on how much can be done in a single clock cycle. In such a case, the unnecessary delay time taken by the delay can be a serious obstacle to the improvement.
Thus, it is desirable on one hand to be able to estimate the length of the clock routing accurately so that the delay with just an appropriate delay time can be selected, and on the other hand to make the clock routing as short as possible so that the clock skew can be minimized.
However, as shown in FIG. 6, a conventional standard cell has flip-flops F/F scattered in numbers of lines R as a result of designing, so that the clock routings 1.sub.1, 1.sub.2, 1.sub.3, 1.sub.4, and 1.sub.5 becomes long and complicated, and neither an accurate estimation of the clock routing length nor minimization of the clock routing has been possible.